1/10 february 2002 n high speed: f max = 185 mhz (typ.) at v cc =5v n low power dissipation: i cc =4 m a (max.) at t a =25 c n high noise immunity: v nih =v nil = 28% v cc (min.) n power down protection on inputs n symmetrical output impedance: |i oh |=i ol = 8 ma (min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 5.5v n pin and function compatible with 74 series 16374 n improved latch-up immunity n low noise: v olp = 0.9v (max.) description the 74vhc16374 is an advanced high-speed flip flop with 3 state outputs non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. these 16 bit d-type flip-flop is controlled by two clock inputs (ck) and two output enable inputs (noe). the device can be used as two 8-bit flip-flops or one 16-bit flip-flop. on the positive transition of the clock, the q outputs will be set to the logic state that were setup at the d inputs. while the (oe) input is low, the outputs will be in a normal logic state (high or low logic level); while oe is high, the outputs will be in a high impedance state. the output control does not affect the internal op- eration of flip-flops; that is, the old data can be re- tained or the new data can be entered even while the outputs are off. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v. all inputs and outputs are equipped with protec- tion circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74vhc16374 16-bit d-type flip flop with 3-state outputs non inverting order codes package tube t & r tssop 74VHC16374TTR tssop pin connection
74vhc16374 2/10 input equivalent circuit pin description truth table x : don't care z : high impedance iec logic symbols pin no symbol name and function 1 1oe 3 state output enable input (active low) 2, 3, 5, 6, 8, 9, 11, 12 1q0 to 1q7 3-state outputs 13, 14, 16, 17, 19, 20, 22, 23 2q0 to 2q7 3-state outputs 24 2oe 3 state output enable input (active low) 25 2ck clock input (low-to-high edge trigger) 36, 35, 33, 32, 30, 29, 27, 26 2d0 to 2d7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1d0 to 1d7 data inputs 48 1ck clock input (low-to-high edge trigger) 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0v) 7, 18, 31, 42 v cc positive supply voltage inputs outputs oe ck d q hxx z l x no change lll lhh
74vhc16374 3/10 logic diagram this logic diagram has not to be used to estimate propagation delays absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied recommended operating conditions 1) v in from 30% to 70% of v cc symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current -20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 75 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 5.5 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 1) (v cc = 3.3 0.3v) (v cc = 5.0 0.5v) 0 to 100 0to20 ns/v
74vhc16374 4/10 dc specifications symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 to 5.5 0.7v cc 0.7v cc 0.7v cc v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 to 5.5 0.3v cc 0.3v cc 0.3v cc v oh high level output voltage 2.0 i o =-50 m a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 m a 2.9 3.0 2.9 2.9 4.5 i o =-50 m a 4.4 4.5 4.4 4.4 3.0 i o =-4 ma 2.58 2.48 2.4 4.5 i o =-8 ma 3.94 3.8 3.7 v ol low level output voltage 2.0 i o =50 m a 0.0 0.1 0.1 0.1 v 3.0 i o =50 m a 0.0 0.1 0.1 0.1 4.5 i o =50 m a 0.0 0.1 0.1 0.1 3.0 i o =4 ma 0.36 0.44 0.55 4.5 i o =8 ma 0.36 0.44 0.55 i oz high impedance output leakage current 5.5 v i =v ih or v il v o =v cc or gnd 0.25 2.5 5 m a i i input leakage current 0to 5.5 v i = 5.5v or gnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i =v cc or gnd 44040 m a
74vhc16374 5/10 ac electrical characteristics (input t r =t f = 3ns) (*) voltage range is 3.3v 0.3v (**) voltage range is 5.0v 0.5v note 1 : parameter guaranteed by design. t solh =|t plhm -t plhn |, t sohl =|t phlm -t phln | capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /16 (per latch) symbol parameter test condition value unit v cc (v) c l (pf) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t plh t phl propagation delay time ck to q 3.3 (*) 15 9 15 1 17 1 17 ns 3.3 (*) 50 10.6 16.2 1 18.5 1 18.5 5.0 (**) 15 5.4 9.1 1 10.1 1 10.1 5.0 (**) 50 6.9 10.1 1 11.5 1 11.5 t pzl t pzh output enable time 3.3 (*) 15 8 13 1 15 1 15 ns 3.3 (*) 50 9.6 14.9 1 16 1 16 5.0 (**) 15 5.1 9.1 1 10 1 10 ns 5.0 (**) 50 6.6 10.1 1 11.5 1 11.5 t plz t phz output disable time 3.3 (*) 50 11.8 15.5 1 17 1 17 ns 5.0 (**) 50 6.1 10.5 1 11.5 1 11.5 t w pulse width (ck) high or low 3.3 (*) 555 ns 5.0 (**) 555 t s setup time dn to ck high or low 3.3 (*) 4.5 4 4 ns 5.0 (**) 333 t h hold time dn to le high or low 3.3 (*) 222 ns 5.0 (**) 222 f max maximum clock frequency 3.3 (*) 80 130 70 70 mhz 5.0 (**) 130 185 110 110 t oslh t oshl output to output skew time (note 1) 3.3 (*) 50 1.5 1.5 1.5 ns 5.0 (**) 50 1 1 1 symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 2.5 10 10 10 pf c out output capacitance 4pf c pd power dissipation capacitance (note 1) 5.0 f in = 10mhz 21 pf
74vhc16374 6/10 dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 5.0v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 5.0v. inputs under test switching: 5.0v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. test circuit c l = 15/50 pf or equivalent (includes jig and probe capacitance) r l =r1=1k w or equivalent r t =z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 5.0 c l =50pf 0.6 0.9 v v olv -0.9 -0.6 v ihd dynamic high voltage input (note 1, 3) 5.0 3.5 v v ild dynamic low voltage input (note 1, 3) 5.0 1.5 v test switch t plh ,t phl open t pzl ,t plz v cc t pzh ,t phz gnd
74vhc16374 7/10 waveform 1 propagation delays, setup and hold times, maximum clock frequency (f=1mhz; 50% duty cycle) waveform 2: output enable and disable time (f=1mhz; 50% duty cycle)
74vhc16374 8/10 waveform 3 : clock pulse widths (f=1mhz; 50% duty cycle)
74vhc16374 9/10 dim. mm. inch min. typ max. min. typ. max. a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 12.4 12.6 0.408 0.496 e 7.95 8.25 0.313 0.325 e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0 8 0 8 l 0.50 0.75 0.020 0.030 tssop48 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7065588a
74vhc16374 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
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